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基于FPGA的UART设计实现 Introduction UniversalAsynchronousReceiver/Transmitter(UART)isaserialcommunicationprotocolbetweentwodevices.Itiswidelyusedinmanyelectronicsystemstoenablecommunicationbetweendeviceswithdifferentinterfacesanddatarates.TheUARTprotocolincludesasetofstartandstopbitstogenerateastartandstopsignalforeachdatabytetransmitted.Thedataisthentransmittedinaserialmanner,witheachbitbeingshiftedoutinaspecificorderandataspecificrate.Inthispaper,wediscussthedesignandimplementationofaUARTprotocolusingFPGAtechnology. FPGATechnology FieldProgrammableGateArray(FPGA)technologyprovidesaflexibleandreconfigurableplatformfordigitalcircuitdesignandimplementation.Itconsistsofalargenumberofconfigurablelogicblocksthatcanbeusedtoimplementanydigitalcircuit.FPGAshavesignificantadvantagesoverotherprogrammablelogicdevices,suchasCPLDsandASICs,intermsofflexibility,speed,andpowerconsumption. UARTDesign TheUARTdesignconsistsoftwomainparts:transmitterandreceiver.Thetransmitterconvertsparalleldataintoserialdataandsendsittothereceiver.Thereceiverconvertstheserialdatabackintoparalleldataandsendsittothedestination. TransmitterDesign Thetransmitterdesignincludesthefollowingcomponents: 1.Paritygeneration:Parityisamethodoferrordetectionusedinserialcommunicationprotocols.Itisanextrabitsentwitheachdatabytetoensurethatthenumberofonesinthebyteisevenorodd.Theparitybitisgeneratedbasedonthedatabeingsentandaddedtothedatabeforetransmission. 2.Baudrategeneration:Baudrateistherateatwhichdataistransmittedinaserialcommunicationsystem.Itdeterminesthenumberofbitstransmittedpersecond.Thebaudrateisgeneratedusingaclocksignalandabaudrategeneratorcircuit. 3.Startbitgeneration:Thestartbitisthebeginningofadatatransmissionsession.Italertsthereceiverthatanewbyteofdataisabouttobetransmitted. 4.Stopbitgeneration:Thestopbitistheendofadatatransmissionsession.Itindicatesthereceiverthatthebyteofdatahasbeentransmittedandcommunicationcanbeterminated. ReceiverDesign Thereceiverdesignincludesthefollowingcomponents: 1.Paritychecking: