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基于IDDQ扫描的SOC可测性设计 Introduction: AsthecomplexityanddensityofSystemonChip(SoC)designshaveincreased,sohasthechallengeoftestingthesedesigns.OneofthekeychallengesintestingSoCdesignsisthedifficultyinidentifyinganddiagnosingfaultsinthedesign.Inthiscontext,detectingfaultsinthedesignhasbecomeacriticalaspect,whichaddstothecomplexityoffutureSoCdesigns.IDDQtestingisconsideredanefficienttechniquetodetectinternaldefectsindigitalcircuitsandcanbeappliedtoimprovetheoverallqualityandreliabilityofSoCdesigns. IDDQTesting: IDDQtestingisatechniquethatmeasuresthecurrentconsumptionofacircuitwhenallinputsareheldatastablestate.TheIDDQtestdeterminesthequiescentcurrent(currentinthesteadystate)ofadigitalcircuitandidentifiesfaultsthatarenotdetectedbyothertraditionaltests.Itidentifiesdefectsintheinterconnects,shorts,opencircuits,andstuck-atfaults. ManySoCdesignsincludemultiplecoresthatareintegratedintoasinglechip.Thesecorescommunicatewitheachotherthroughacommoninterconnect.WhentestingacomplexdesignlikeanSoC,testingtheinterconnectcanbemorechallengingthantestingthelogiccoresthemselves.ApplyinganIDDQtesttotheinterconnectcandetectdefectsthatarenotvisiblethroughothertests. IDDQ-basedscandesigntechnique: TheIDDQ-basedscandesigntechniqueaddressestestabilityanddiagnosisissuesforlarge-scaleSoCdesigns.TheIDDQscandesigntechniquetransformsthecircuitintoaformthatisamenabletotestanddiagnosticprograms.Thisapproachinvolvesinsertingscanchainsintothedesignthatprovideaccesstotheinternalcomponentsofthecircuit. Thescanchainscapturethevaluesoftheinternalstatesofthecircuitduringtesting,whichallowthegenerationofIDDQsignatures.TheIDDQsignaturescanthenbecomparedtoreferencesignaturestoidentifyanyfaultsinthecircuit.AsignatureanalyzerisusedtocomparetheseIDDQsignatures.Thiscomparisonproblemcanalsobecapturedmathematicallyandcanbesolvedusingvariousdataminingtechniques. AdvantagesoftheIDDQ-basedscandesigntechnique: ThereareseveraladvantagesofusingtheIDDQ-basedscandesigntechniqueinSoCtesting.Theseinclude: 1.Increasedfaultcoverage