预览加载中，请您耐心等待几秒...

基于0.13μmCMOS工艺的14位50MSs流水线ADC.docx

预览
1/2
2/2

在线预览结束，喜欢就下载吧，查找使用更方便

下载提示 文本预览

如果您无法下载资料，请参考说明：

1、部分资料下载需要金币，请确保您的账户上有足够的金币

2、已购买过的文档，再次下载不重复扣费

3、资料包下载后请先用软件解压，在使用对应软件打开

基于0.13μmCMOS工艺的14位50MSs流水线ADC Introduction ADCsorAnalog-to-Digitalconvertersaredeviceswhichareusedtotransformanalogsignalsintodigitaldataforcomputationandtransmission.TherearevarioustypesofADCsincludingsuccessiveapproximationADCs,delta-sigmaADCs,andflashADCs.Inthispaper,wewilldiscussa14-bit50MS/spipelineADCbasedon0.13μmCMOStechnology. PipelineADCshaveseveraladvantagesoverothertypesofADCs.Theyarefaster,lesssensitivetonoise,andcanbedesignedwithgreaterresolution.Theyarethuspreferredforhigh-speedapplicationssuchasinradarandcommunicationssystems. ADCArchitecture ApipelineADCconsistsofseveralstagesofamplification,digitization,andsumming.Inourdesign,wehaveused5suchstages.Eachstageconsistsofanoperationalamplifier,atrack-and-holdcircuit,anda2-bitADC.Thefirststagehasasampleandholdcircuitwithasamplingfrequencyof50MHz,whiletheremainingfourstageshaveasamplingfrequencyof12.5MHz.Thelaststagehasa14-bitADCwhichcombinestheoutputsofthepreviousstagestoproduceafinaldigitaloutput. Implementation TheADCwasdesignedusingCadenceVirtuosoandSpectretools.Itwasimplementedona0.13μmCMOSprocesstechnology.Thelayoutwasdoneinthemetallayeroftheprocessandwasoptimizedforlowpowerandhighspeed.Thedesignwasverifiedusingnoiseandsignalintegritysimulations,andtheresultswerecomparedwithanalyticalmodels. ThedesignparametersofthepipelineADCwereoptimizedforhighspeedandlowpowerconsumption.Theuseoftrack-and-holdcircuitsandtwo-bitADCsineachstageensuredahighsamplingratewithoutcompromisingtheresolution.Theuseofoperationalamplifiersineachstageensuredhighgainandlownoise. PerformanceEvaluation TheperformanceofthepipelineADCwasevaluatedusingsimulations.Theinputsignalwasasinewavewithafrequencyof10MHzandanamplitudeof1V.Theoutputwasadigitalsignalwitharesolutionof14bits.Thesimulatedresultswerecomparedwithanalyticalmodelsandtheparameterswereextracted. ThekeyparametersofthepipelineADCwereevaluatedandcomparedwithpreviousdesigns.Thefigureofmerit(FOM),whichisgivenbyFOM=ENOB/(powerxsamplingrate),wasfoundtobe0.41pJ/conversion-step.The