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WSNPLL频率综合器中分频器的设计.docx

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WSNPLL频率综合器中分频器的设计 Introduction Frequencysynthesizersareessentialcomponentsinmanywirelesscommunicationsystems.Inwirelesssensornetworks(WSN),frequencysynthesizersplayacriticalroleinachievingreliablecommunicationwithlowpowerconsumption.Aphase-lockedloop(PLL)isthemostcommonlyusedfrequencysynthesizerinWSNs.ThePLLisaclosed-loopfeedbackcontrolsystemthatgeneratesanoutputsignalwithastablefrequencyandphaserelationshipwithrespecttoaninputreferencesignal.ThefrequencyandphaseofthePLLoutputsignalcanbeadjustedbychangingthefeedbackloopparameters,suchasthephasedetector,loopfilter,andvoltage-controlledoscillator(VCO).Inthispaper,wefocusonthedesignofthePLLfrequencydividerforWSNapplications. PLLFrequencyDividers ThePLLfrequencydividerisacriticalcomponentinthePLLsystemthatgeneratesadivided-downversionoftheVCOoutputsignal.Thefrequencydividerreducesthehigh-frequencyVCOoutputsignaltoalowerfrequencythatcanbeusedasareferencesignalforthephasedetector.Thefrequencydivisionratioisdeterminedbythedividercircuit'sdesignandcanbeadjustedtoachievethedesiredoutputfrequency.Thefrequencydividercanbeimplementedusingeitherdigitaloranalogcircuits. DigitalPLLFrequencyDivider ThedigitalPLLfrequencydividerisbasedonacounterthatcountsthenumberofcyclesoftheVCOoutputsignalandgeneratesapulsewhenthedesireddivisionratioisreached.Thepulsetriggersaflip-flopthatgeneratesasquarewavewithafrequencythatisequaltotheVCOfrequencydividedbythedivisionratio.Thesquarewaveisthenpassedthroughalow-passfiltertoremovethehigh-frequencyharmonics,resultinginthedesiredreferencesignalforthephasedetector.Thedigitalfrequencydividerisfastandaccurate,makingitsuitableforhigh-frequencyapplications.However,itisalsopower-hungryandgeneratessignificantnoiseduetoitsdigitalnature. AnalogPLLFrequencyDivider TheanalogPLLfrequencydividerisbasedonafrequencydividercircuitthatdividestheVCOoutputfrequencybythedesireddivisionratio.Thefrequencydividercanbeimplementedusingvarioustopologies,suchasthedivide-by-2flip-flop,theJohnsoncounter,orthedivide-by-3counter.