基于FPGA的自动打铃系统的设计与实现.doc

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自动打铃系统设计说明书

学生姓名：罗衡
学号：
专业班级：电子0９-２BF
报告提交日期：2０１１-11-28

湖南理工学院物电学院

目录
一、题目及要求简介···············································1
设计题目····················································1
2.总体要求简介················································1
二、设计方案说明·················································1
三、各部分功能介绍及程序·······································２
1。系统框图····················································２
2.选择的FPGA芯片及配置·······································2
3。各模块（元件)说明··········································２
四、仿真结果·····················································4
1。计时进位····················································4
2。手动校时····················································5
３。六点整闹铃··················································5
五、说明··························································5
1.输入激励信号说明············································5
２．输出结果说明················································6
六、源程序························································6
1．顶层模块····················································6
模式控制子模块··············································7
计时及调整子模块············································8
闹铃及调整子模块············································1０
显示子模块··················································１1
七、参考文献·····················································１４

一、设计题目及要求简介
１.设计题目
基于FPGA的自动打铃系统的设计与实现
2.总体要求简介
（1)基本计时和显示功能
①２4小时制显示
②动态扫描显示
③显示格式：８8—88－88
（2)能设置当前时间（含时、分）
（3）能实现基本打铃功能，上午０6:00起床铃,打铃5秒
设计方案说明
本系统采用自顶向下的模块化设计方法,将数字闹钟按照功能实现分为模式控制模块、计时及调整模块、闹铃及调整模块、显示模块。系统调整部分软件控制流程示意图如图２-１所示.
↓

开始

mode
↓

↓

1
2
↓

0
校时功能
↓

↓

闹铃功能

计时功能
→

调整小时

←
→
LD_hour亮
调整小时

turn
切换
切换
↔
↔
→

LD_min亮
调整分钟

调整分钟

change
↓

↓

LD_alert亮
→
返回计时
返回计时

图2－1

各部分功能介绍及程序
1。系统框图
顶层电路主要由ＦPGA实现，输出信号接到八位数码管、LED指示灯及扬声器上，系统框图如图３-1所示。
Altera
▃
Alert
LD_alert
LD_hour
LD_min
sel
decodeout
clk
clk_1k
mode
turn
change

顶
层
模
块
▶

▶

▶

八位数码管显示模块

图3—1
选择的FPGＡ芯片及