基于FPGA的自动打铃系统的设计与实现.doc

PAGE-1-自动打铃系统设计说明书学生姓名:罗衡学号:14092500060专业班级：电子09—2BF报告提交日期：2011—11—28湖南理工学院物电学院目录一、题目及要求简介···············································1设计题目····················································12.总体要求简介················································1二、设计方案说明·················································1三、各部分功能介绍及程序·······································21.系统框图····················································22.选择的FPGA芯片及配置·······································23。各模块（元件）说明··········································2四、仿真结果·····················································41。计时进位····················································42。手动校时····················································53。六点整闹铃··················································5五、说明··························································51.输入激励信号说明············································52.输出结果说明················································6六、源程序························································61。顶层模块····················································6模式控制子模块··············································7计时及调整子模块············································8闹铃及调整子模块············································10显示子模块··················································11七、参考文献·····················································14PAGE\*MERGEFORMAT-12-一、设计题目及要求简介1。设计题目基于FPGA的自动打铃系统的设计与实现2.总体要求简介(1）基本计时和显示功能①24小时制显示②动态扫描显示③显示格式:88-88—88（2）能设置当前时间（含时、分）（3）能实现基本打铃功能,上午06：00起床铃，打铃5秒设计方案说明本系统采用自顶向下的模块化设计方法,将数字闹钟按照功能实现分为模式控制模块、计时及调整模块、闹铃及调整模块、显示模块。系统调整部分软件控制流程示意图如图2—1所示。↓开始mode↓↓12↓0校时功能↓↓闹铃功能计时功能→调整小时←→LD_hour亮调整小时turn切换切换↔↔→LD_min亮调整分钟调整分钟change↓↓LD_alert亮→返回计时返回计时图2-1各部分功能介绍及程序1.系统框图顶层电路主要由FPGA实现，输出信号接到八位数码管、LED指示灯及扬声器上,系统框图如图3—1所示。Altera▃AlertLD_alertLD_hourLD_minseldecodeoutclkclk_1kmodeturnchange顶层模块▶▶▶八位数码管显示模块图3-1选择的FPGA芯片及配置本系统选择ACEX1K系列的EP1K10TC100-3芯片，由于FPGA器件是基于SRAM结构的,具有易失性，在此采用被动串行配置(PS)方式，由外部的计算机控制配置过程,使用USB-Blaster下载电缆下载程序。3。各模块（元件)说明3.1顶层文件端口说明modulealarmclock（c