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EDA实验VHDL程序.doc

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(1)1011状态机 libraryieee; useieee.std_logic_1164.all; entityasdfis port(xi,rst,clk:bit; zo:outbit); endasdf; architectureasdfofasdfis typestateis(zero,one,two,three,four); signalpre_state,nx_state:state; begin process(rst,clk) begin if(rst='1')then pre_state<=zero; elsif(clk'eventandclk='1')then pre_state<=nx_state; endif; endprocess; process(pre_state) begin casepre_stateis whenzero=>zo<='0'; if(xi='1')thennx_state<=one; elsenx_state<=zero; endif; whenone=>zo<='0'; if(xi='0')thennx_state<=two; elsenx_state<=one; endif; whentwo=>zo<='0'; if(xi='1')thennx_state<=three; elsenx_state<=zero; endif; whenthree=>zo<='0'; if(xi='1')thennx_state<=four; elsenx_state<=two; endif; whenfour=>zo<='1'; if(xi='1')thennx_state<=one; elsenx_state<=two; endif; endcase; endprocess; endasdf; 2模24计数器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; entitycouter2is port(rst,clk:instd_logic; Q:outstd_logic_vector(0to4)); endcouter2; architecturecouter2ofcouter2is begin process(rst,clk) variabled1:integerrange0to23; begin if(rst='0')then d1:=0; elsif(clk'eventandclk='1')then d1:=d1+1; if(d1>23)then d1:=0; endif; endif; Q<=conv_std_logic_vector(d1,5); endprocess; endcouter2; 3百进制数码管显示 libraryieee; useieee.std_logic_1164.all; entitycounter1is port(clk,rst:instd_logic; output1,output2:outstd_logic_vector(0to6)); endcounter1; architecturebhvofcounter1is begin process(rst,clk) variablet1,t2:integerrange0to10; begin if(rst='1')then t1:=0;t2:=0; elsif(clk'eventandclk='1')then t1:=t1+1; if(t1>9)thent1:=0;t2:=t2+1; if(t2>9)thent2:=0; endif; endif; endif; caset1is when0=>output1<="1111110"; when1=>output1<="0110000"; when2=>output1<="1101101"; when3=>output1<="1111001"; when4=>output1<="0110011"; when5=>output1<="1011011"; when6=>output1<="1011111"; when7=>output1<="1110000"; when8=>output1<="1111111"; when9=>output1<="1111011"; whenothers=>null; endcase; caset2is when0=>output2<="1111110"; when1=>output2<="0110000"; when2=>output2<="1101101"; when3=>output2<="1111001"; when4=>outp