EDA-常见实例源程序代码vhdl.pdf

第4章用VHDL程序实现常用逻辑电路
4.1组合逻辑电路设计
4.1.1基本逻辑门
libraryieee;
useiee.std_logic_1164.all;
entityjbmis
port(a,b:inbit;
f1,f2,f3,f4,f5,f:outbit);
endjbm;
architectureaofjbmis
begin
f1<=aandb;--构成与门
f2<=aorb;--构成或门
f<=nota;--构成非门
f3<=anandb;--构成与非门
f4<=anorb;--构成异或门
f5<=not(axorb);--构成异或非门即同门
end;
4.1.2三态门
libraryieee;
useieee.std_logic_1164.all;
entitytri_sis
port(enable:instd_logic;
datain:instd_logic_vector(7downto0);
dataout:outstd_logic_vector(7downto0));
endtri_s;
architecturebhvoftri_sis
begin
process(enable,datain)
begin
ifenable='1'then
dataout<=datain;
else
dataout<="ZZZZZZZZ";
endif;
endprocess;
endbhv;
4.1.33-8译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecoder3_8is
port(a,b,c,g1,g2a,g2b:instd_logic;
y:outstd_logic_vector(7downto0));
enddecoder3_8;
architectureaofdecoder3_8is
signaldz:std_logic_vector(2downto0);
begin
dz<=c&b&a;
process(dz,g1,g2a,g2b)
begin
if(g1='1'andg2a='0'andg2b='0')then
casedzis
when"000"=>y<="11111110";
when"001"=>y<="11111101";
when"010"=>y<="11111011";
when"011"=>y<="11110111";
when"100"=>y<="11101111";
when"101"=>y<="11011111";
when"110"=>y<="10111111";
when"111"=>y<="01111111";
whenothers=>y<="XXXXXXXX";
endcase;
else
y<="11111111";
endif;
endprocess;
4.1.4优先编码器
libraryieee;
useieee.std_logic_1164.all
entitycoderis
port(din:instd_logic_vector(0to7);
output:outstd_logic_vector(0to2));
endcoder;
architecturebehaveofcoderis
signalsint:std_logic_vevtor(4downto0);
begin
process(din)
begin
if(din(7)='0')then
output<="000";
elsif(din(6)='0')then
output<="100";
elsif(din(5)='0')then
output<="010";
elsif(din(4)='0')then
output<="110";
elsif(din(3)='0')then
output<="001";
elsif(din(2)='0')then
output<="101";
elsif(din(1)='0')then
output<="011";
else
output<="111";
endif;
endprocess;
endbehav;
4.1.57段码译码器
libraryieee;
useieee.std_logic_1164.all
entitydecl7sis
port(a:instd_logic_vector(3downto0);
led7s:outstd_logic_vector(6downto0));
enddecl7s;
architecturebehaveofdecl7sis
begin
process(a)
begin
caseais
when"0000"=>led7s<="0111111";
when"000