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pci引脚定义 pci 接口定义.docx

2024-11-04

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pci引脚定义 Pin+5V+3.3VUniversalDescriptionA1TRSTTestLogicResetA2+12V+12VDCA3TMSTestMdeSelectA4TDITestDataInputA5+5V+5VDCA6INTAInterruptAA7INTCInterruptCA8+5V+5VDCA9RESV01ReservedVDCA10+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A11RESV03ReservedVDCA12GND03(OPEN)(OPEN)GroundorOpen(Key)A13GND05(OPEN)(OPEN)GroundorOpen(Key)A14RESV05ReservedVDCA15RESETResetA16+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A17GNTGrantPCIuseA18GND08GroundA19RESV06ReservedVDCA20AD30Address/Data30A21+3.3V01+3.3VDCA22AD28Address/Data28A23AD26Address/Data26A24GND10GroundA25AD24Address/Data24A26IDSELInitializationDeviceSelectA27+3.3V03+3.3VDCA28AD22Address/Data22A29AD20Address/Data20A30GND12GroundA31AD18Address/Data18A32AD16Address/Data16A33+3.3V05+3.3VDCA34FRAMEAddressorDataphaseA35GND14GroundA36TRDYTargetReadyA37GND15GroundA38STOPStopTransferCycleA39+3.3V07+3.3VDCA40SDONESnoopDoneA41SBOSnoopBackoffA42GND17GroundA43PARParityA44AD15Address/Data15A45+3.3V10+3.3VDCA46AD13Address/Data13A47AD11Address/Data11A48GND19GroundA49AD9Address/Data9A52C/BE0Command,ByteEnable0A53+3.3V11+3.3VDCA54AD6Address/Data6A55AD4Address/Data4A56GND21GroundA57AD2Address/Data2A58AD0Address/Data0A59+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A60REQ64Request64bit???A61VCC11+5VDCA62VCC13+5VDCA63GNDGroundA64C/BE[7]#Command,ByteEnable7A65C/BE[5]#Command,ByteEnable5A66+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A67PAR64Parity64???A68AD62Address/Data62A69GNDGroundA70AD60Address/Data60A71AD58Address/Data58A72GNDGroundA73AD56Address/Data56A74AD54Address/Data54A75+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A76AD52Address/Data52A77AD50Address/Data50A78GNDGroundA79AD48Address/Data48A80AD46Address/Data46A81GNDGroundA82AD44Address/Data44A83AD42Address/Data42A84+5V+3.3VSignalRail+VI/O(+5Vor+3.3V)A85AD40Address/Data40A86AD38Address/Data38A87GNDGroundA88AD36Address/Data36A89AD34Address/Data34A90GNDGroundA91AD32Address/Data32A92RESReservedA93GNDGroundA94RESReservedB1-12V-12VDCB2TCKTestClockB3GNDGroundB4TDOTestDataOutputB5+5V+5VDCB6+5V+5VDCB7INTBInterruptBB8INTDInterruptDB9PRSNT1Reserved

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