UART模块Verilog代码.docx

uart.v
`timescale1ns/100ps

moduleuart(dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn,din,tbre,tsre,wrn,sdo);

outputtbre;
outputtsre;
outputsdo;
input[7:0]din;
inputrst;
inputclk16x;
inputwrn;
inputrxd;
inputrdn;
output[7:0]dout;
outputdata_ready;
outputframing_error;
outputparity_error;

rcvru1(dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn);

txmitu2(din,tbre,tsre,rst,clk16x,wrn,sdo);

endmodule
rcvr.v
`timescale1ns/1ns

modulercvr(dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn);

inputrxd;
inputclk16x;
inputrst;
inputrdn;
output[7:0]dout;
outputdata_ready;
outputframing_error;
outputparity_error;

regrxd1;
regrxd2;
regclk1x_enable;
reg[3:0]clkdiv;
reg[7:0]rsr;
reg[7:0]rbr;
reg[3:0]no_bits_rcvd;

regdata_ready;

regparity;
regparity_error;
regframing_error;

wireclk1x;

assigndout=!rdn?rbr:8'bz;

always@(posedgeclk16xorposedgerst)
begin
if(rst)
begin
rxd1<=1'b1;
rxd2<=1'b1;
end
else
begin
rxd1<=rxd;
rxd2<=rxd1;
end
end

always@(posedgeclk16xorposedgerst)
begin
if(rst)
clk1x_enable<=1'b0;
elseif(!rxd1&&rxd2)
clk1x_enable<=1'b1;
elseif(no_bits_rcvd==4'b1100)
clk1x_enable<=1'b0;
end

always@(posedgeclk16xorposedgerstornegedgerdn)
begin
if(rst)
data_ready=1'b0;
elseif(!rdn)
data_ready=1'b0;
else
if(no_bits_rcvd==4'b1011)
data_ready=1'b1;
end

always@(posedgeclk16xorposedgerst)
begin
if(rst)
clkdiv=4'b0000;
elseif(clk1x_enable)
clkdiv=clkdiv+1;
end

assignclk1x=clkdiv[3];

always@(posedgeclk1xorposedgerst)
if(rst)
begin
rsr<=8'b0;
rbr<=8'b0;
parity<=1'b1;
framing_error=1'b0;
parity_error=1'b0;
end
else
begin
if(no_bits_rcvd>=4'b0001&&no_bits_rcvd<=4'b1000)//4'b1001
begin
/*MSBFirst
rsr[0]<=rxd2;
rsr[7:1]<=rsr[6:0];
parity<=parity^rsr[7];
*/

/*LSBFirst*/
rsr[7]<=rxd2;
rsr[6:0]<=rsr[7:1];
parity<=parity^rsr[0];

end
elseif(no_bits_rcvd==4'b1001)//4'b1010
begin
rbr<=rsr;
end
elseif(!parity)
parity_error=1'b1;
elseif((no_bits_rcvd==4'b1011)&&(rxd2!=1'b1))
framing_error=1'b1;
else
framing_error=1'b0;
end

always@(posedgeclk1x