Verilog编写的CIC代码.doc

Verilog编写的CIC代码

//internalclk>=8*outputclk

modulecicmodule
(inputclk,internalclk,outputclk,preset,datainput,dataoutput);
parameterDataWidth=18;

parameterOutputDiv=4;//OutputDiv=(order-1)*ln(outputclk/inputclk)/ln(2)

inputinputclk;
inputinternalclk;
inputoutputclk;
inputpreset;
inputsigned[(DataWidth-1):0]datainput;
outputsigned[(DataWidth-1):0]dataoutput;

//registers
reginputclkperiod;
reg[2:0]statecount;
regsigned[(DataWidth-1):0]inputreg;

//--stage1(comb)signals,gain=2->+1bit
regsigned[DataWidth:0]int0;

//--stage2(comb)signals,gain=2->+1bit
regsigned[DataWidth+1:0]int1;

//--stage3(comb)signals,gain=2->+1bit
regsigned[DataWidth+2:0]int2;
regsigned[DataWidth+2:0]tempreg0;
regsigned[DataWidth+2:0]tempreg1;

//--stage4(integrator)signals,gain=2->+1bit
regsigned[DataWidth+4:0]int3;

//--stage5(integrator)signals,gain=0.5->-1bit
regsigned[DataWidth+5:0]int4;

//--stage6(integrator)signals,gain=4->+2bit
regsigned[DataWidth+7:0]int5;

regsigned[DataWidth+7:0]addInputA;
regsigned[DataWidth+7:0]addInputB;
regsigned[DataWidth+7:0]addInputBsig;
regaddsubSelect;
wiresigned[DataWidth+7:0]addOutput;

//Add/sun
always@(addInputBoraddsubSelect)
begin
if(addsubSelect)
addInputBsig=-addInputB;
else
addInputBsig=addInputB;
end

//Add
assignaddOutput=addInputA+addInputBsig;

//Outputassign
assigndataoutput=int5>>>OutputDiv;

//Clkoperations
always@(posedgeinputclkorposedgeoutputclkorposedgepreset)
begin
if(preset==1)
inputclkperiod=1;
elseif(inputclk==1)
inputclkperiod=1;
else
inputclkperiod=0;
end

always@(posedgeinputclkorposedgepreset)
begin
if(preset==1'b1)
inputreg=0;
else
inputreg=datainput;
end

always@(posedgeinternalclkorposedgeinputclkorposedgepreset)
begin
if(preset==1)
statecount=0;
elseif(inputclk==1)
statecount=0;
else
statecount=statecount+1;
end

always@(negedgeinternalclkorposedgepreset)
begin
if(preset==1)begin
tempreg0=0;
tempreg1=0;
int0=0;
int1=0;
int2=0;
int3=0;
int4=0;
int5=0;
end
elsebegin
case(statecount)
3'd0:begin
if(inputclkperiod==1)begin
tempreg0=