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DRAMTECHNOLOGY.pdf

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7DRAMTECHNOLOGY OVERVIEW DRAM(DynamicRandomAccessMemory)isthemainmemoryusedforalldesktopandlarger computers.EachelementaryDRAMcellismadeupofasingleMOStransistorandastorage capacitor(Figure7-1).Eachstoragecellcontainsonebitofinformation.Thischarge,however, leaksoffthecapacitorduetothesub-thresholdcurrentofthecelltransistor.Therefore,thecharge mustberefreshedseveraltimeseachsecond. BitLine WordLineTransistor Capacitor Plate Source:ICE,"Memory1997"19941 Figure7-1.DRAMCell HOWTHEDEVICEWORKS Thememorycelliswrittentobyplacinga“1”or“0”chargeintothecapacitorcell.Thisisdone duringawritecyclebyopeningthecelltransistor(gatetopowersupplyorVCC)andpresenting eitherVCCor0V(ground)atthecapacitor.Thewordline(gateofthetransistor)isthenheldat groundtoisolatethecapacitorcharge.Thiscapacitorwillbeaccessedforeitheranewwrite,a read,orarefresh. Figure7-2showsasimplifiedDRAMdiagram.Thegatesofthememorycellsaretiedtothe rows.Theread(orwrite)ofaDRAMisdoneintwomainstepsasillustratedinFigure7-3.The row(X)andcolumn(Y)addressesarepresentedonthesamepadsandmultiplexed.Thefirst stepconsistsofvalidatingtherowaddressesandthesecondstepconsistsofvalidatingthe columnaddresses. INTEGRATEDCIRCUITENGINEERINGCORPORATION7-1 DRAMTechnology AddressX RowDecode Pads CAS RAS Y Data Sense DataAmplifier Data Sense DataAmplifier Output Dout BufferData YDecodeSense DataAmplifier Input D inBuffer Data Sense DataAmplifier Source:ICE,"Memory1997"22430 Figure7-2.SimplifiedDRAMDiagram RAS AddressRowColumn CAS StepIStepII RowAccessColumnAccess Source:ICE,"Memory1997"22431 Figure7-3.DRAMAccessTiming 7-2INTEGRATEDCIRCUITENGINEERINGCORPORATION DRAMTechnology FirstStep:RowAddresses RowaddressesarepresentonaddresspadsandareinternallyvalidatedbytheRAS(RowAddress Access)clock.Abarontopofthesignalnamemeansthissignalisactivewhenitisatalowlevel. TheXaddressesselectonerowthroughtherowdecode,whilealltheothernon-selectedrows remainat0V.Eachcelloftheselectedrowistiedtoasenseamplifier.Asenseampli