八位数码管的动态显示VHDL程序.doc

libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entityseg_displayis
port(clk:instd_logic;--定义动态扫描时钟信号
reset:instd_logic;--定义复位信号
ledag:outstd_logic_vector(6downto0);--定义数码管的七段输出信号
del:outstd_logic_vector(2downto0)--定义八位数码管位置显示信号
);
endseg_display;
--------------------------------------------------------------------
architecturewhphtaoofseg_displayis
signalclk1Khz:std_logic;--数码管扫描时钟
signalclk1hz:std_logic;--计数时钟
signalcq:std_logic_vector(3downto0);--计数值
begin

PROCESS(clk)--产生1hz信号
variablecnt:INTEGERRANGE0TO49999999;
BEGIN
IFclk='1'ANDclk'eventTHEN
IFcnt=49999999THENcnt:=0;
ELSE
IFcnt<25000000THENclk1hz<='1';
ELSEclk1hz<='0';
ENDIF;
cnt:=cnt+1;
ENDIF;
ENDIF;
endprocess;

PROCESS(clk)--产生1Khz信号
variablecnt1:INTEGERRANGE0TO49999;
BEGIN
IFclk='1'ANDclk'eventTHEN
IFcnt1=49999THENcnt1:=0;
ELSE
IFcnt1<25000THENclk1khz<='1';
ELSEclk1khz<='0';
ENDIF;
cnt1:=cnt1+1;
ENDIF;
ENDIF;
endprocess;

process(clk1hz,reset)
variablecqi:std_logic_vector(3downto0);

begin
ifreset='0'thencqi:=(others=>'0');--计数器异步复位
elsifclk1hz'eventandclk1hz='1'then--检测时钟上升沿
ifcqi<15thencqi:=cqi+1;
elsecqi:=(others=>'0');
endif;
--endif;
endif;
cq<=cqi;--计数值向端口输出
endprocess;

process(clk1KHZ)--数码管动态扫描
variabledount:std_logic_vector(2downto0);
begin
ifclk1kHZ'eventandclk1kHZ='1'then--检测时钟上升沿
dount:=dount+1;--计数器dount累加
endif;
del<=dount;
endprocess;
process(cq)--数码管显示
begin
casecqis
when"0000"=>ledag<="0111111";
when"0001"=>ledag<="0000110";
when"0010"=>ledag<="1011011";
when"0011"=>ledag<="1001111";
when"0100"=>ledag<="1100110";
when"0101"=>ledag<="1101101";
when"0110"=>ledag<="1111101";
when"0111"=>ledag<="0000111";
when"1000"=>ledag<="1111111";
when"1001"=>ledag<="1101111";
when"1010"=>ledag<="1110111";
when"1011"=>ledag<="1111100";
when"1100"=>ledag<="0111001";
when"1101"=>ledag<="1011110";
when"1110"=>ledag<="1111001";
when"1111"=>ledag<="1110001";
whenothers=>null;
endcase;
end